Description
Due to a problem in the Quartus® II software, the ModelSim simulation software may generate this error when compiling SystemVerilog code created by the State Machine Editor. The code created by the State Machine Editor does not comply with the SystemVerilog specification. However, note that the Quartus II synthesis does not generate an error for this code.
Resolution
To work around problem, edit the SystemVerilog code created by the State Machine Editor. Change the declaration of the signal to a variable type such as reg.
This problem is scheduled to be fixed in a future release of the Quartus II software.