Article ID: 000084784 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How are differential SSTL and HSTL I/O standards implemented on Stratix and Stratix GX devices?


Description Differential SSTL and HSTL have unique implementations for Stratix® and Stratix GX devices depending on the type of function desired (input, output, clocking, etc). The following list details the specifics.

Differential HSTL Dedicated Clocks:
Inputs: Differential HSTL clock inputs use a dedicated differential buffer (no VREF association). As such, differential HSTL inputs are not subject to the pad placement rules that affect single ended signals. Further, differential HSTL clock inputs are
not subject to the pad placement rules that would be applied to other differential signals such as LVDS.
Outputs: Differential HSTL clock outputs are implemented using two single ended outputs and must adhere to the single-ended pad placement rules and not the differential restrictions.

Differential SSTL Dedicated Clocks:
Inputs: Not supported.
Outputs: Differential SSTL dedicated clock outputs are implemented identically to differential HSTL clock outputs. See above for more information.

Differential SSTL/HSTL non-dedicated I/Os:
Differential HSTL or SSTL support on regular IOs (sometimes referred to as pseudo-differential) is implemented by using two single ended HSTL or SSTL inputs or outputs. Further, because these are actually multiple single ended signals emulating differential, these signals are bound by the single-ended pad placement restrictions and do not adhere to the differential restrictions.

Related Products

This article applies to 2 products

Stratix® FPGAs
Stratix® GX FPGA



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