Article ID: 000084739 Content Type: Error Messages Last Reviewed: 04/30/2014

Warning (12283): Assignment INPUT_TERMINATION on transceiver refclk clk buf/pin is not supported

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description In Arria® V, Cyclone® V and Stratix® V devices the INPUT_TERMINATION assignment cannot be used on transceiver pins.
Resolution

Change the INPUT_TERMINATION of pin <pcie_refclk_name> to \'Transceiver Dedicated Refclk Pin Termination\' and select the appropriate Quartus® Settings File(QSF) assignments.
Refer to the Altera Transceiver PHY IP Core User Guide for more information on how to use these assignments. 

As an example, the .qsf file will appears as below if the option DC_COUPLING_INTERNAL_100_OHM is used:

set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_EXTERNAL_100_OHMS -to <pcie_refclk_name>

Related Products

This article applies to 12 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.