Article ID: 000084696 Content Type: Troubleshooting Last Reviewed: 08/08/2022

Why does the Stratix® IV GX/GT transceiver CDR, configured in automatic locked mode, keep the rx_freqlocked signal asserted in any other mode except PCIe mode?



For an explanation of why the Stratix® IV GX/GT CDR unit may be keeping the rx_freqlocked signal asserted in any other mode except PCIe mode, refer to the Stratix IV GX Errata Sheet (PDF) and Stratix IV GT Errata Sheet (PDF).


    A patch is available to provide a software solution for the Quartus® II software versions 9.1 SP2 and 10.0 SP1. Download and install the appropriate patch from the links below. The software solution to resolve this problem is fully integrated into the Quartus II software versions later than 10.0 SP1, so no patch installation is required.

    Note that the software patches are not compatible with certain previous patches indicated below. If you are using one of these incompatible patches, review the alternate solution involving the reset sequence illustrated in Figure 1 and described below, or file a service request at if you require a compatible patch.



    If the transceiver is configured in basic mode and it requires the rx_signaldetect signal, such as for SATA or SAS protocol, you must rerun the parameter editor, regenerate the IP function, and recompile your design. You can also run the following from the command line to regenerate the IP function without going through the parameter editor:

    qmegawiz -silent <altgx_file>

    where altgx_file is the name of the IP function variation file.

    If the transceiver is configured in any other mode except PCIe mode and the rx_signaldetect signal is not required, you can rerun the Quartus II software assembler step without the need to perform a full compilation.

    Alternate Solution

    As an alternative to the above software solutions, you can apply the reset sequence solution described below and illustrated in the waveforms in Figure 1 to resolve the problem.

    Figure 1. Reset Sequence Waveforms

    1. Assert the rx_analogreset and the rx_digitalreset signals.
    2. The rx_freqlocked[0..n-1] signals will go low, indicating that the transceivers are locking to the reference clock (lock to reference).
    3. Deassert the rx_analogreset signal. Ensure data is present at the receiver inputs before deasserting the rx_analogreset signal.
    4. The rx_freqlocked[0..n-1] signals will go high, indicating the transceivers are locking to data.
    5. About 4 µs (tLTD_Auto) after the last rx_freqlocked signal goes high, deassert the rx_digitalreset signal.

    Related Products

    This article applies to 2 products

    Stratix® IV GT FPGA
    Stratix® IV GX FPGA



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