Article ID: 000084695 Content Type: Troubleshooting Last Reviewed: 12/14/2015

Possible Timing Closure Difficulty for QDR II Interfaces on Arria 10 Devices

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

QDR II interfaces on Arria 10 devices may experience difficulty achieving timing closure. This problem is most evident when core-to-periphery and periphery-to-core transfers approach 333 MHz, with PLL VCO of less than 600 MHz.

Resolution

The workaround for this problem is to do one of the following:

  • Try compiling with multiple seeds.
  • Use a PLL VCO value of greater than 600 MHz.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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