Critical Issue
Description
You might have a problem with the user 0 clock frequency when you generate the Arria V/Cyclone V Hard Processor System component for any Arria V SoC device with the I3 speed grade. For these devices, if you set the Configuration/HPS-to-FPGA user 0 clock frequency parameter to 125.0 MHz, Qsys generates the component with a higher clock frequency, and you see a warning similar to the following:
"Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 125.0 MHz, but only achieved 131.25 MHz
If the resulting clock frequency is greater than 125 MHz, you cannot use U-boot to configure the FPGA with the raw binary file (.rbf).
Resolution
Set the Configuration/HPS-to-FPGA user 0 clock frequency to 123 MHz or less.