Article ID: 000084638 Content Type: Troubleshooting Last Reviewed: 07/25/2023

In simulation of the Stratix® V Reconfiguration Controller, why do my ATX Calibration Registers all read "DEADBEEF"?

Environment

    Quartus® II Subscription Edition
    L-Tile H-Tile Transceiver ATX PLL Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Simulation of the transceiver ATX PLL calibration registers in Stratix® V GX devices is not supported. However, the calibration processes are fully functional in silicon.

Resolution

You should not attempt to access these registers in simulation.

Related Products

This article applies to 4 products

Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® V FPGAs
Stratix® V GS FPGA

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