Article ID: 000084629 Content Type: Error Messages Last Reviewed: 09/11/2012

Warning: Compensate clock of PLL <"PLL instance name>" has been set to LVDS Clock


  • Quartus® II Subscription Edition

    You will see this warning when implementing the ALTLVDS_RX or ALTLVDS_TX megafunctions with the external PLL mode option enabled for the Stratix® III, Stratix IV, Arria® II, HardCopy® III, and HardCopy IV device families.

    When using the dedicated SERDES available in these device families, the Quartus® II software automatically sets the compensated clock to the LVDS clock / DIFFIOCLK which is used as the high speed clock for the SERDES circuitry.  Although you should set the PLL operation mode to source-synchronous compensation, there is currently no option in the ALTPLL megafunction available to specify the compensated clock when using dedicated SERDES circuitry. 


    You can safely ignore this warning.  It reports the compensated clock has been set correctly for your design when using the ALTLVDS_RX or ALTLVDS_TX megafunctions with external PLL mode enabled. 

    However, if you wish to avoid this warning you can edit the ALTPLL variation file to specify the compensate clock.

    For VHDL, locate the compensate_clock parameter in the GENERIC MAP section and enter "LVDSCLK".

    For Verilog, locate the altpll_component.compensate_clock parameter in the defparam section and enter "LVDSCLK".

    Related Products

    This article applies to 9 products

    Stratix® III FPGAs
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV E FPGA
    Arria® II GX FPGA
    Arria® II GZ FPGA
    HardCopy™ III ASIC Devices
    HardCopy™ IV GX ASIC Devices
    HardCopy™ IV E ASIC Devices