Article ID: 000084601 Content Type: Troubleshooting Last Reviewed: 07/10/2013

Serial Digital Interface (SDI) and SDI II Transceiver Reference Clock Fitter Error

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    SDI and SDI II designs targeting Cyclone V devices will encounter fitter error when you connect the transceiver reference clock, xcvr_refclk, to an output counter of fractional phase-locked loop (fpll). You will get the following error message:

    "Could not place global or regional clock driver."

    Resolution

    To work around this issue, follow these steps:

    Open the file <design_name>_0002.v and search for altera_xcvr_reset_control module.

    The transceiver reference clock, xcvr_refclk, drives the clock input, although the connection is from the PHY adapter, phy_adapter.

    Create another input clock at the top level of the SDI or SDI II core. The clock port of altera_xcvr_reset_control connects to this newly created input clock. Externally, this input clock can be driven by another clock source or another output counter of the fpll.

    This issue is fixed in version 13.0 SP1 of the SDI and SDI II MegaCore functions.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

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