Critical Issue
Description
If you use the ATX PLL and soft reset controller with a Gen2 Arria V GZ Hard IP for PCI Express IP Core, you may observe link training speed changes issues. This issue occurs because this configuration incorrectly uses hard offset cancellation at startup instead of soft offset cancellation.
Resolution
The workaround is to select the CMU PLL and the hard reset controller for Gen2 variants of the Arria V GZ Hard IP for PCI Express IP Core.