Article ID: 000084587 Content Type: Troubleshooting Last Reviewed: 12/11/2015

Link Training Issues when Using the ATX PLL and Soft Reset Controller with Gen2 Arria V GZ Hard IP for PCI Express IP Core

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you use the ATX PLL and soft reset controller with a Gen2 Arria V GZ Hard IP for PCI Express IP Core, you may observe link training speed changes issues. This issue occurs because this configuration incorrectly uses hard offset cancellation at startup instead of soft offset cancellation.

    Resolution

    The workaround is to select the CMU PLL and the hard reset controller for Gen2 variants of the Arria V GZ Hard IP for PCI Express IP Core.

    Related Products

    This article applies to 1 products

    Arria® V GZ FPGA

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