During simulation of a Qsys-generated VHDL design that includes DDR2 or DDR3 external memory cores with ALTMEMPHY, the 64-bit version of Mentor Graphics ModelSim SE 6.6d may issue a fatal error similar to the following:
#**Note: (vsim-3812) Design is being optimized...
#**Fatal: Unexpected signal: 11.
Use the 32-bit version of Mentor Graphics ModelSim SE 6.6d
or use the
-novopt option with the