Article ID: 000084550 Content Type: Troubleshooting Last Reviewed: 10/09/2015

Invalid pin multiplexing configurations in HPS Qsys systems for Cyclone V SoC devices


  • Quartus® II Subscription Edition

    Critical Issue


    If you create a hard processor system (HPS) in Qsys that targets a Cyclone V SoC device with the U19 package and a 484 pin count, the following peripheral pin multiplexing parameter settings in Qsys might result in compilation errors:

    • If you use a Secure Digital/MultiMediaCard (SD/MMC) Controller with eight data pins in your design, or
    • If you enable the USB0 Controller, or
    • If you enable the queued serial peripheral interface (QSPI) Flash Controller by setting QSPI pin multiplexing to HPS I/O Set 1 and then setting QSPI mode to two Slave Selects (2 SS) or more.

    Design your HPS Qsys system with the following limitations in mind:

    • Pins MIXED1IO21, FLASHIO4, FLASHIO5, FLASHIO6, and FLASHIO7 are not available on the U19 package.
    • The U19 package only supports a SD/MMC Controller with up to four data pins.
    • Do not enable the USB0 Controller; the U19 package does not support the USB0 Controller. Instead, enable the USB1 Controller and use the SDR mode.
    • Enable the QSPI Flash Controller using HPS I/O Set 1 with one SS or using HPS I/O 0 with any number of SS.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs