Description
Assuming the input reference clock to the PLL is stable, the PLL Locked signal will not toggle while the PLL establishes lock. The general purpose PLLs in Stratix® V, Stratix IV, Stratix III, Arria® 10, Arria V, Arria II, Cyclone® V, Cyclone IV and Cyclone III devices have a hardened hysteresis filter which will prevent the Locked port from toggling.