Article ID: 000084543 Content Type: Error Messages Last Reviewed: 09/10/2013

Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This warning will be generated for designs using Cyclone® V devices in the Quartus® II software version 13.0sp1 when using differential and single-ended I/O standards in the same I/O bank.  However, this warning may also be generated by mistake for banks that only contain single-ended I/O pins.

     

    Resolution

    The warning can be ignored if there are no LVDS, RSDS, or mini-LVDS signals in banks that only contain single-ended I/O standards.

    The critical warning is scheduled to be fixed in a future version of the Quartus II software so that it is only generated in valid cases.

    Related Products

    This article applies to 6 products

    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA

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