Article ID: 000084523 Content Type: Troubleshooting Last Reviewed: 03/31/2014

Why don't I see the h2f_rst_n signal assert in HPS simulation?

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software BFM simulation model, asserting the "h2f_rst_n" signal does not drive the "h2f_rst_n" signal. This causes unexpected interconnect behavior and Qsys interconnect logic is not reset.

    This problem affects simulation only.

    Resolution

    To workaround this problem,

    1. Modify "INITIAL_RESET_CYCLES" parameter in "submodules/<qsys-system-name>_<HPS-instance-name>_fpga_interfaces.sv" file to greater than 0
    2. Assign clock (f2h_axi_clk) to the "h2f_reset_inst" instance. 

    Simulation Code:
    ----------------
    altera_avalon_reset_source #(
      .ASSERT_HIGH_RESET(0),
      .INITIAL_RESET_CYCLES(0)    <======== (1)  change "0" to 100 such as .INITIAL_RESET_CYCLES(100)
    ) h2f_reset_inst (
      .reset(h2f_rst_n),
      .clk(\'0)   <======== (2)  change \'0 to clock signal such as .clk(f2h_axi_clk)
    );
    ----------------

    This problem is scheduled to be fixed in a future release of Quartus II software.

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Arria® V SX SoC FPGA

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