Article ID: 000084514 Content Type: Troubleshooting Last Reviewed: 01/26/2015

What timing constraints should I apply for the clock signal generated from the Max 10 internal oscillator?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Depending on your configuration of the Max® internal oscillator you should apply one of the two timing constraints below:

For a Clock Frequency setting of 116MHz:

create_clock -name test -period 116MHz [get_pins -compatibility {<path to instancve>|int_osc_0|oscillator_dut|clkout}]

For a Clock Frequency setting of 55MHz:

create_clock -name test -period 55MHz [get_pins -compatibility {<path to instancve>|int_osc_0|oscillator_dut|clkout}]

Resolution

This constraint is scheduled to be automatically added in a future release of the Quartus® II software.

Related Products

This article applies to 1 products

Intel® MAX® 10 FPGAs

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