Article ID: 000084504 Content Type: Troubleshooting Last Reviewed: 02/15/2019

Why does the transceiver pll_locked signal deassert when rx_analogreset is asserted during simulation of Cyclone IV GX devices?

Environment

  • Cyclone® IV GX FPGA
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Description

The transceiver pll_locked signal deasserts when rx_analogreset is asserted during simulation of Cyclone®  IV GX devices due to an incorrect simulation model.

The transceiver rx_analogreset signal incorrectly resets the MPLL and causes the pll_locked signal to deassert in the Quartus® II Software Version 9.1-SP2.

The following patches are available to fix this issue.

This issue will be fixed in a future version of the Quartus II Software.

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