Article ID: 000084498 Content Type: Troubleshooting Last Reviewed: 08/22/2016

Why are the clock constraints for ALTPLL incorrect when using derive_pll_clocks?

Environment

    Intel® Quartus® Prime Pro Edition
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Description Due to a problem in the Quartus® Prime software version 16.0 and 16.0 Update 1, you may see that the phase value is incorrect in the constraints generated by derive_pll_clocks. This occurs when using the ALTPLL IP.
Resolution This problem is fixed beginning with the Quartus Prime software version 16.0 Update 2.

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Intel® Programmable Devices

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