Article ID: 000084497 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How can I make sure that all the output clocks from the Stratix® PLL have the correct phase, when the PLL is powered up without an input clock toggling?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description There might be cases where the PLL is fully powered up, but the input clock has not started toggling yet. If this is the case in your system, once the input clock starts toggling, assert ARESET for 10ns and then allow the PLL to lock onto the input clock. This will guarantee that all the clock outputs from the PLL will have the correct phase after the PLL locks onto the input clock.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs

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