Article ID: 000084490 Content Type: Troubleshooting Last Reviewed: 03/31/2023

Why does avl_ready deassert after avl_write_req is asserted in my DDR3 and DDR2 SDRAM High Performance Controller II IP?

Environment

    Quartus® II Subscription Edition
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Description

When error correction code (ECC) is enabled, you will see avl_ready de-assert after avl_write_req is asserted increasing the Write latency. It is because the controller needs to wait for incoming data (deassert ready signal) and then decide if read-modify-write operation is required during command loading.

Resolution

This behavior will not occur if ECC is disabled.

This problem is fixed starting with the Quartus® II software version 12.0.

Related Products

This article applies to 9 products

Arria® II GX FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA
Stratix® V E FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA
Stratix® III FPGAs

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