Article ID: 000084474 Content Type: Troubleshooting Last Reviewed: 08/10/2015

Incorrect ACP IDs Listed in Arria 10 and Cyclone 10 HPS Technical Reference Manuals

Environment

  • Quartus® II Subscription Edition
  • DMA
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Arria V Hard Processor System Technical Reference Manual and Cyclone V Hard Processor System Technical Reference Manual list incorrect values for the HPS peripheral master input IDs in the Accelerator Coherency Port (ACP) ID mapper. The “HPS Peripheral Master Input IDs” table contains incorrect ID values.

    Resolution

    Use v14.0 or later of the Hard Processor System Technical Reference Manual. v14.0 and later show the correct ACP IDs, as follows:

    HPS Peripheral Master Input IDs
    Interconnect MasterID
    DMA00000xxxx001
    EMAC010000xxxx001
    EMAC110000xxxx010
    USB0100000000011
    USB1100000000110
    NAND1xxxxxxxx100
    DAP000000000100
    SD/MMC100000000101
    FPGA-to-HPS Bridge0xxxxxxxx000
    L2M00xxxxxxxx010
    TMC100000000000

    ID values are binary. The letter x denotes variable ID bits that the master passes with each transaction.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs