Article ID: 000084454 Content Type: Troubleshooting Last Reviewed: 11/15/2011

Reset Synchronization Problem

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 10.0 Version Fixed: 11.0

FPGA Intellectual Property

Ethernet

Version Found: 10.0 Version Fixed: 11.0

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The reset_rx_clk and reset_tx_clk signals do not synchronize to rx_clk and tx_clk.

This issue affects variants of MAC function with 1000BASE-X/SGMII PCS and embedded PMA.

Resolution

No workaround.This issue is fixed in version 11.0 of the Triple-Speed Ethernet MegaCore function.

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