Article ID: 000084437 Content Type: Troubleshooting Last Reviewed: 05/16/2023

Why is my Channel 0 Write Data reaching all of my Native PHY channels in my multichannel design?

Environment

    Quartus® II Subscription Edition
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Description

Due to a problem in the Quartus® II software version 14.1, the Channel 0 reconfiguration data is incorrectly written to all channels in the instance. This problem occurs when a multichannel Native PHY instance uses a multichannel, independent Avalon memory mapped interface for dynamic reconfiguration.

Resolution

To work around this problem,

  1. Open the file <variant_name>/alt_xcvr_native_avmm_nf.sv.
  2. Find line 158.
  3. Change it from:

Current Line 158:

assign avmm_writedata[ig*8 :8] = arb_writedata[7:0];
 

To:

Corrected Line 158:

assign avmm_writedata[ig*8 :8] = arb_writedata[ig*32 :8];

 

This problem is scheduled to be fixed in a future release of the Quartus software.

Related Products

This article applies to 4 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA

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