Description
In table 2 of AN141, there are two SDRAM address configurations shown, 8x11, and 10x12. In each configuration, the bits in the top row indicate row address, and the bits in the bottom row indicate column address.
The address bits of the EPXA devices' SDRAM controller are always mapped in the following order starting with bit 2:
- Column Address
- Bank Address
- Row Address
Resolution
Address bits 1..0 are used to decode the byte mask enable pins DQM[3..0]