Article ID: 000084411 Content Type: Troubleshooting Last Reviewed: 05/10/2022

Application Note 141 Excalibur Solutions - Using the SDRAM Controller, table 2, which address bits are SDRAM row address, and which are column

Environment

  • Quartus® II Subscription Edition
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    Description

    In table 2 of AN141, there are two SDRAM address configurations shown, 8x11, and 10x12. In each configuration, the bits in the top row indicate row address, and the bits in the bottom row indicate column address.

    The address bits of the EPXA devices' SDRAM controller are always mapped in the following order starting with bit 2:

    • Column Address
    • Bank Address
    • Row Address

     

    Resolution

    Address bits 1..0 are used to decode the byte mask enable pins DQM[3..0]

    Related Products

    This article applies to 1 products

    Excalibur™

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