Article ID: 000084393 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I use a clock control block to choose between one enhanced PLL output and one fast PLL output in Stratix II and Stratix II GX devices for my design?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, you can not use a clock control block to choose between one enhanced PLL output and one fast PLL output in Stratix® II and Stratix II GX devices. Global and regional resources used by enhanced and fast PLLs are different.

You will be able to use the outputs of two different enhanced PLLs or two different fast PLLs on the same side of the device that share global and regional resources.

For more information on global and regional clock network connections used by each PLL, refer to Stratix II Handbook chapter PLLs in Stratix II and Stratix II GX devices (PDF).

Related Products

This article applies to 2 products

Stratix® II GX FPGA
Stratix® II FPGAs

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