Article ID: 000084362 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Why does the Transmitter PLL and/or CDR not lock after power-up in Stratix IV and Arria II GX Transceivers.

Environment

  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
  • Arria® II GX FPGA
  • Arria® II FPGAs
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Altera has identified this issue in designs compiled using the Quartus® II software version 9.0 SP2 or earlier versions.

    Impacted devices- Stratix®  IV GX, Stratix®  IV GT, Arria®  II GX

    Solution - For all designs, except the two cases listed below, download the following patch on top of the Quartus® II software version 9.0 SP2 and recompile the design.

    Windows-

    Quartus II software version 9.0 SP2 Windows Patch 2.53

    Linux-

    Quartus II software version 9.0 SP2 Linux Patch 2.53

    Exception Case 1: All instantiated transceiver channels on either side of the device are configured as "Transmitter Only" AND not connected to a dynamic reconfiguration controller (altgx_reconfig Megafunction)

    Exception Case 2: No transceiver channels are instantiated on left side of the device but one or more dedicated refclk pins from the left side are used as FPGA clock input pin. The same case applies for the right side of the device.

    Solution for Exception Case 1 and Case 2: Instantiate a dummy receiver channel on each side of the device that meets the conditions listed in Exception Case 1 or Case 2. Download the patch using the links listed above. Install the patch on Quartus II software version 9.0 SP2 and recompile your design.

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