Article ID: 000084352 Content Type: Troubleshooting Last Reviewed: 12/03/2012

In 40GbE and 100GbE MAC and PHY IP Cores, the Quartus II Software Reports Minimum Pulse Width Violations for Some 10-Gbps PHY Clock Signals

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In 40GbE and 100GbE MAC and PHY IP cores, the Quartus II software reports minimum pulse width violations for 10-Gbps Low Latency PHY designs on the following clock signals:

    x_top|sv_low_latency_phy_inst|sv_low_latency_phy_inst|sv_xcvr_low_latency_phy_nr_inst|sv_xcvr_10g_custom_native_inst|sv_xcvr_native_insts[0].gen_bonded_group_native.sv_xcvr_native_inst|inst_sv_pcs|ch[1].inst_sv_pcs_ch|inst_stratixv_hssi_rx_pld_pcs_interface|pld10grxclkout~CLKENA0|outclk x_top|sv_low_latency_phy_inst|sv_low_latency_phy_inst|sv_xcvr_low_latency_phy_nr_inst|sv_xcvr_10g_custom_native_inst|sv_xcvr_native_insts[0].gen_bonded_group_native.sv_xcvr_native_inst|inst_sv_pcs|ch[1].inst_sv_pcs_ch|inst_stratixv_hssi_rx_pld_pcs_interface|wys|pld10grxpldclk
    Resolution

    This issue is fixed in the 12.1 Quartus software release of the IP core.

    For the 12.0 release of the IP core, please ignore these paths. These minimum pulse width violations are for false paths.

    Related Products

    This article applies to 2 products

    Stratix® IV FPGAs
    Stratix® V FPGAs

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