Article ID: 000084351 Content Type: Troubleshooting Last Reviewed: 02/13/2023

Is there a known issue with the mif file generated for PLL reconfiguration, for Intel® Arria® V, Cyclone® V, and Stratix® V devices?

Environment

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Description

Yes, when the Altera_PLL Megawizard is used to generate a Memory Initialization File (.mif) for Arria® V, Cyclone® V or Stratix® V devices, the generated file will contain the incorrect DATA Bandwidth field.

Resolution

Update the DATA bandwidth field to the correct value.  The location of the field is shown in table 7 of 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores. The correct bandwidth setting may be found using the PLL Reconfiguration Calculator.

Related Products

This article applies to 14 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Stratix® V E FPGA
Cyclone® V SX SoC FPGA
Cyclone® V E FPGA
Stratix® V GS FPGA
Cyclone® V ST SoC FPGA
Arria® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Cyclone® V SE SoC FPGA
Cyclone® V GT FPGA
Stratix® V GT FPGA

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