This problem may occur because of the way Analysis & Synthesis parses the VHDL parameter values for two or more VHDL instances that are configured with the same configuration. Analysis & Synthesis uses one parameter value for all VHDL instances of the same entity, even when you intend to use different parameter value for each instance.
This incorrect synthesis problem occurs in the Quartus® II software versions 6.0 and earlier, and is is fixed beginning with the Quartus II software version 6.1.
As an example of when this problem can occur, the following design uses the same "my_entity_cfg" configuration for all the instances of "my_entity".
CONFIGURATION my_top_cfg OF my_top IS
FOR top_arc
FOR ALL: my_entity
USE CONFIGURATION work.my_entity_cfg;
END FOR;
END FOR;
END my_top_cfg;
For this design, you can create "inst1" and "inst2" for “my_entity” in your top-level design and pass two different parameter values to both inst1 and inst2. In the example below, "inst1" and "inst2" are instantiated in the top-level design. The top-level design passes value “one” to inst1 and value “two” to inst2.
inst1: my_entity
GENERIC MAP(type => one)
PORT MAP(
data0 => a,
data1 => b,
result => one_out);
inst2: my_entity
GENERIC MAP(type => two)
PORT MAP(
data0 => a,
data1 => b,
result => two_out);
In this example, Quartus II software versions 6.0 and earlier use the “two” parameter value for both "inst1" and "inst2", which can result in incorrect design behavior.
To work around this issue in versions 6.0 and earlier, create a copy of the “my_entity_cfg” configuration called “my_entity_cfg1”. Change the top-level design to use the two different configuration names, as in the following change to the previous example:
FOR inst1: my_entity
USE CONFIGURATION work.my_entity_cfg;
END FOR;
FOR inst2: my_entity
USE CONFIGURATION work.my_entity_cfg1;
END FOR;