Article ID: 000084335 Content Type: Troubleshooting Last Reviewed: 11/25/2013

Can Half-Rate DDR or DDR2 Altmemphy Datapaths be interleaved in Stratix III and Stratix IV devices?

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Description

No, in Stratix® III and Stratix IV devices the half-rate resynchronization clock is cascaded from one DQ group to the next directly in the IOE. Hence Half-Rate Datapaths using the Altera Altmemphy Must Not be Interleaved with each other.

This Requirement does not effect Full-Rate Altmemphy Datapaths. Refer to AN 435: Using DDR and DDR2 SDRAM in Stratix III and Stratix IV Devices (PDF) for more information.

Related Products

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Stratix® III FPGAs

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