Most device families will state in the handbook that manual clock switchover requires both clocks to be running:
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Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
With this requirement, manual clock switchover cannot be used for clock redundancy applications where you need to switch to a backup clock in the event the primary clock fails.
When clock redundancy is required, you can use automatic clock switchover, but you must ensure both clocks are running when the FPGA is configured. If you cannot meet this requirement, you can disable the clock switchover feature in the PLL, and instead insert a clock control block in your design on the clock path between the input pins and the PLL. This will allow you to manually select between two clock pins without any requirement that the clocks are running.
Note, by inserting a clock control block on the input path the clock feeding the PLL will be driven over a global network, so there may be increased jitter and the clock path cannot be fully compensated.