Article ID: 000084325 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any changes in the Stratix PLL VCO limits in the Quartus® II software version 2.2 SP1?


Description Yes. Based upon silicon characterization data, the following changes were made to the Stratix PLL (Enhanced PLL/Fast PLL for all Stratix devices) specifications in the Quartus II software version 2.2 SP1:

Prior to Version 2.2 SP1:

The VCO range for both EPLL and FPLL was set between 300-1000MHz, pending silicon characterization.

The following changes were made to Stratix PLL Timing in the Quartus II software version 2.2 SP1:

For Enhanced PLLs (EPLLs):

The Quartus II software version 2.2 SP1 will enforce the 300-800MHz VCO range as specified in the Stratix device family data sheet for -5 and -6 speed grades. The VCO range for the -7 speed grade is 300-600 MHz.

For Fast PLLs (FPLLs):

The Quartus II software version 2.2 SP1 will continue to support the 300-1000 MHz VCO range when the FPLL is used for general purposes. The higher VCO range enables more flexibility in choosing multiplication and division factors in Quartus. When the FPLL is used in Source Synchronous mode, the VCO frequency range doesn't change from the data sheet spec of 300-840 MHz.

The Stratix device family data sheet will be updated to reflect the new specs for the -5,-6 and -7 speed grade devices.

Workarounds For Affected Designs:

  1. Since the Quartus II software version 2.2 SP1 supports the 300-1000 MHz VCO range for the FPLLs, if possible, the EPLLs can be ported over to FPLLs by checking the "Use Fast PLL" check-box on page 1 of the ALTPLL mega-wizard. Note that, this might not be possible if the design needs the use of the dedicated external clock outputs that are only available on the EPLLs.

    Also, the above cannot be met if the PLL uses any of the EPLL specific features like Clock switchover, Programmable bandwidth, PLL Reconfiguration, Spread Spectrum etc, or if the clock input/output pins are locked down in the design.

  2. Another workaround is to split up the output frequencies between 2 or more EPLLs.


    Inclk to EPLL = 33.3333 MHz, Desired outputs at 66.6666 MHz, 100 MHz and 166.66 MHz. LCM of these output frequencies is 999.9Mhz which will result in a no-fit.

For the above combination:

Quartus II Version 2.2 - Meets the Input/Output frequency combinations.

Quartus II Version 2.2 SP1 - Cannot meet and could offer output clock frequencies as shown below:

  1. 66.666 MHz, 111.11 MHz, 166.66 MHz (VCO at 333 MHz) or
  2. 62.5 MHz, 100.00 MHz, 166.66 MHz (VCO at 500 MHz)

In the example above, the 100 MHz output can be moved to another EPLL separate from the one that outputs 66.66 MHz and 166.66 MHz outputs.

Related Products

This article applies to 1 products

Stratix® FPGAs