Article ID: 000084324 Content Type: Troubleshooting Last Reviewed: 08/28/2012

Why are the transceiver clocks in my Cyclone IV GX PCI Express design not automatically generated correctly when using the derive_pll_clocks command in the Quartus II software version 11.1?

Environment

  • Quartus® II Subscription Edition
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    Description

    Due to a problem in the Quartus® II software version 11.1, the derive_pll_clocks command may fail to generate all the necessary clocks for Cyclone® IV GX PCI Express designs. You may see warnings similar to the following in the TimeQuest timing analyzer:

    Warning (332087): The master clock for this clock assignment could not be derived.
    Clock: <user hierarchy>|hiptxclkout was not created.
    Warning (332086): Ignoring clock spec: <user hierarchy>|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0 Reason:
    Clock derived from ignored clock: <user hierarchy>|transmit_pcs0|hiptxclkout.  Clock assignment is being ignored.
    Warning (332086): Ignoring clock spec: <user hierarchy>|cyclone_iii.cycloneiv_hssi_pcie_hip|coreclkout Reason:
    Clock derived from ignored clock: <user hierarchy>|cyclone_iii.cycloneiv_hssi_pcie_hip|pclkch0.  Clock assignment is being ignored.

    Due to this problem, certain transceiver clocks may not be correctly constrained in your design and the IP may not function correctly in hardware.

    Resolution

    A patch is available to fix this problem for the Quartus II software version 11.1. Download and install Patch 0.09 from the appropriate link below.

    This problem is fixed beginning with the Quartus II software version 11.1 SP1.

    Related Products

    This article applies to 1 products

    Cyclone® IV GX FPGA

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