Article ID: 000084323 Content Type: Troubleshooting Last Reviewed: 03/04/2013

Why are the output clocks from my altera_pll twice the expected output frequency in simulation?

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 12.0 and later,  Altera PLL Megafunction instances may generate PLL output clocks with twice the expected frequency when simulated. 

    Note:  This is a simulation only issue.

     

    Resolution

    To workaround this issue follow the steps below:

    1. Open the generated simulation model in a text editor <variation name>_sim/<variation name>.<vho/vo>
    2. Search for the text pll_vco_div
    3. Update the pll_vco_div parameter to 2 (may be incorrectly set to 1)

    For example:

    • Verilog : <variation name>_sim/<variation name>.vo

    Before:

    <variation name>_altera_pll_altera_pll_<instance ID>.pll_vco_div = 1,

    After:

    <variation name>_altera_pll_altera_pll_<instance ID>.pll_vco_div = 2,

    • VHDL: <variation name>_sim/<variation name>.vho

    Before:

    pll_vco_div => 1,

    After:

    pll_vco_div => 2,

    This problem is fxed beginning with the Quartus II software version 12.1.

    Related Products

    This article applies to 14 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Cyclone® V GX FPGA
    Stratix® V GS FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA

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