You may see lower than expected maximum VCCIO current in the PowerPlay Power Analyzer report for the banks which contain address/command pins which are controlled by a hard memory controller when using vectorless estimation. These signals are incorrectly set a static probability of 0 which means that they are analysed as never driving logic-high.
This is due to a problem with the estimation of static probability of the address/command signals from the hard memory controller.
The PowerPlay Power Analyzer assumes that the recommended external termination is fitted when using IO standards that require external termination such as the SSTL standards used by DDRx memory interfaces. Using the external termination to Vtt which SSTL requires, current flows from VCCIO to Vtt when the output drives high and from Vtt to GND when the output drives low.
Due to the problem with the static probability of the address/command output signals, there is no VCCIO current included in the estimate for the address/command signals.
The current estimation for the address/command signals is correct when using simulation results or user-entered default toggle-rate assignments within the PowerPlay Power Analyzer.
You can override the static probability of these ports using the POWER_STATIC_PROBABILITY assignment. Refer to the Quartus Settings File Reference Manual (PDF) for more information on this assignment.
This problem does not affect the PowerPlay Early Power Estimator (EPE) spreadsheet.
This problem will be fixed in a future version of the Quartus® II software.