Article ID: 000084309 Content Type: Troubleshooting Last Reviewed: 12/09/2013

Why do I see a Fatal Error in the Quartus II software after routing my Stratix III PLL output directly to a device output pin?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see a fatal error if you connect a Stratix® III PLL clock output directly to a device output pin.

Resolution

To work around this error either:

  • Remove the connection.
  • Use the PLL output clock to clock a DDIO output register stage that has it\'s data_h port tied to \'1\' and it\'s data_l port tied to \'0\'. This results in the clock signal propagating through the DDIO output stage but removes the direct connection to the pin.

This problem is scheduled to be fixed in a future release of the Quartus II software.

Related Products

This article applies to 1 products

Stratix® III FPGAs

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