Description
This warning may be generated multiple times by the Cadence NC-Sim software when compiling the Stratix® V Verilog HDL libraries for Cadence tools from the Quartus® II software versions 10.1 to 11.1.
It is safe to ignore these warnings.
This problem is scheduled to be fixed in a future release of the Altera Complete Design Suite.
Note:
The Stratix V Verilog HDL libraries for Cadence tools are located in the <Quartus II installation directory>/quartus/eda/sim_lib/cadence directory. For more information, see Guidelines for Compiling Stratix V Libraries in the Quartus II Help version 10.1 and later.