Article ID: 000084291 Content Type: Product Information & Documentation Last Reviewed: 06/29/2014

How should I connect the MIF address bus between the reconfiguration controller and MIF ROM when word addressing is used in Stratix V GX devices?

Environment

  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    MIF addressing is dependent upon the mode selected by bit 1 of address offset 0x1 detailed in the "Streamer Module Internal MIF Register Offsets" table of the PHY IP Userguide.

    The MIF address bus of the reconfiguration controller is 16-bit aligned when word addressing is used. In this case the LSB is unused. When you use the reconfiguration controller in MIF streaming mode, you should connect the address bus to the ROM as shown in the example below:

    reconf_rom rom0(
    .clock(phy_mgmt_clk),
    .address(reconfig_mif_address[9:1]),
    .q(reconfig_mif_readdata));

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