Article ID: 000084286 Content Type: Product Information & Documentation Last Reviewed: 05/09/2023

How do I implement a "One 18 x 19 Multiplication Summed with 36-Bit Input Mode" DSP function in an Intel® Arria® 10 device?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To implement this (or other) advanced Intel® Arria® 10 FPGA digital signal processing (DSP) configuration, use the HDL templates available in the Quartus® II software.

Resolution

For a list of available templates, follow these steps:

  1. Right-click in a VHDL or Verilog HDL file, and select Insert Template.
  2. Select VHDL or Verilog HDL, then select Full Designs > Arithmetic > DSP Features > DSP Features for 20-nm device.

Related Products

This article applies to 4 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.