When does the UniPHY DDR3 IP use an I/O standard of SSTL-15 Class II ?

When the UniPHY DDR3 PHY Settings tab "Memory Clock frequency" parameter is set above 800 MHz, the default DDR3 interface signal I/O standard is set to SSTL-15 Class II to increase the drive strength. The memory datapath and clock signals have an Output Termination assignment of Series 25 ohm with calibration.

These assignments are applied in the standard supported flow of running the <variation_name>_p0_pin_assignments.tcl file after analysis and synthesis.

It is strongly recommended that you perform board level simulations to verify the signal integrity of your DDR3 interface.