The PCIe® HIP (root port) sends the memory read TLP to the endpoint, and then the PCIe HIP (root port) receives the completion TLP from the endpoint. If the endpoint sends a memory read/write TLP to PCIe HIP (root port) but the TLP is not present on the Avalon-ST interface of PCIe HIP. In this case, you need to check if the PCIe HIP (root port) drops the TLP or the TLP is not sent by the endpoint. You can observe the PIPE interface signals of PCIe HIP to check if the TLP is received by the PHY layer of PCIe HIP.
Please set trigger condition as below:
test_out[24] (rxvalid) = '1'
test_out[23] (rxdatak) = '1'
test_out[22:15] (rxdata) = 'fb' (K28.7, Start of TLP)
If the trigger condition can't be met, it means the endpoint does not send the TLP to PCIe HIP (root port).