Article ID: 000084275 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why doesn't my design fit with cascaded PLLs that use the reconfiguration feature?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

There is a problem in the Quartus® II software version 8.1 and earlier related to cascaded PLLs that use the reconfiguration feature in Stratix® III, Cyclone® III, and Stratix IV devices.

The software algorithm that remaps the PLL clock outputs to match suitable counter outputs in the PLL hardware might use incorrect remapping information when a reconfigurable upstream PLL is cascaded to a downstream PLL.  When the software performs an incorrect PLL clock output remapping, the design does not behave as expected and compilation can result in various symptoms, including a no-fit error or a software internal error.

There is a patch available to fix this problem in the Quartus II software version 8.1. Use mySupport to request Quartus II 8.1 patch 0.28 for Windows or Linux, and recompile the design with the patch installed.

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 3 products

Stratix® III FPGAs
Cyclone® III FPGAs
Stratix® IV E FPGA