sdram_CK0 and sdram_CK1, respectively), which are tied through a clock distribution chip (U5) to the EP20K200 CLK_OUT2p pin (pin P5). Therefore, the APEX™ device phase-locked loop (PLL) must generate the SRAM clock signals for all designs using SDRAM in the SODIMM socket. The reason for this layout is because SDRAM is sensitive to clock skew, and the PLL allows complete control of both clock frequency and phase.
To complete your design using SDRAM as a data or program memory location for your Nios-based design, use the MegaWizard® Plug-In Manager (Tools menu) to instantiate a PLL into the top level of your design in the Quartus® II software. Selecting Create a new megafunction variation, and then ALTCLKLOCK (I/O menu) in the Plug-In manager. You can configure the PLL to multiply or divide the input clock to suit your design requirements. For SDRAM operation, activate the "Clock 1" output. Once the software generates the PLL,instantiate it into your design and use the "Clock 1" output of the PLL to drive both the Nios CPU clock input, and output IO pin. The Quartus II Compiler automatically assigns the I/O pin on Clock 1 to the APEX device I/O pin 5 (CLK_OUT2p), which will then be fed automatically to the appropriate pins in the SODIMM connector. This design will ensure that the Nios CPU and SDRAM clocks are within phase. Additionally, you should ensure that unused APEX device I/O pins do not drive to ground. Refer to solution Why do I see an output stuck at ground, or a very weak output signal when using the phase-locked loop (PLL) on my Excalibur™development board featuring the Nios embedded processor?for additional details on making these settings.