Description
You may receive this error when compiling a hierarchical VHDL design. This error occurs when a range is specified for an output or an inout signal in a port mapping.
The following code segment will cause this error:
U1: my_adder
PORT MAP (
f(3 downto 0) => output(3 downto 0);
The correct component instantiation is:
U1: my_adder
PORT MAP (
f => output(3 downto 0);