Article ID: 000084212 Content Type: Troubleshooting Last Reviewed: 01/15/2013

What is the minimum pulse width timing specification of the global reset signal in UniPHY IP?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Global reset in UniPHY IP is connected to the PLL areset port. Therefore the minimum pulse width of the PLL areset port will be the minimum pulse width specification of the PLL areset port.

You can refer to the PLL specification part of the device datasheet.

For example Minimum pulse width on the PLL areset port is 10ns for Stratix® IV device and Stratix® V device.

Related Products

This article applies to 7 products

Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® V GS FPGA
Stratix® V E FPGA

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