Article ID: 000084205 Content Type: Troubleshooting Last Reviewed: 07/10/2013

Serial Digital Interface (SDI) Receiver Locking Problem

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

You may encounter locking problem when any of these signals—enable_hd_search, enable_sd_search, enable_3g_search—is set to low for the SDI receiver in dual standard or triple rate mode.The locking problem is due to the corrupted recovered clock, caused by the improper handling of the transceiver reset.

Resolution

Set the enable_hd_search, enable_sd_search, and enable_3g_search signals to high when using dual standard or triple rate mode.

This issue will not be fixed.

Related Products

This article applies to 4 products

Arria® II FPGAs
Arria® GX FPGA
Stratix® IV FPGAs
Stratix® II GX FPGA

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