Article ID: 000084197 Content Type: Troubleshooting Last Reviewed: 08/06/2014

Why are ECO changes to the D3 Delay Chain 1 not implemented correctly?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® II software version 14.0 and earlier, you may find that ECO changes to the D3 Delay Chain 1 are not implemented correctly. The change does not take effect and no difference is seen in the timing netlist or in hardware.

This problem affects Arria® V and Cyclone® V devices.

Resolution

To work around this problem, do not use the ECO flow to modify the D3 Delay Chain 1 setting.

You can set the D3 Delay chain 1 value by using the D3_DELAY assignment and recompiling the design.

This problem is scheduled to be fixed in a future release of the Quartus II software.

Related Products

This article applies to 11 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Arria® V GT FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.