Article ID: 000084196 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Can a single fPLL output be used as a transceiver reference clock and also drive logic within the fabric on Stratix V GX, Arria V GX, and Arria V GZ devices?

Environment

  • Stratix® V GX FPGA
  • Stratix® V GT FPGA
  • Stratix® V GS FPGA
  • Arria® V SX SoC FPGA
  • Arria® V GZ FPGA
  • Arria® V GX FPGA
  • Arria® V GT FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description No, a single fPLL output cannot be used as a transceiver reference clock source and also drive logic within the fabric on Stratix® V GX, Arria® V GX, and Arria® V GZ devices.
Resolution

To use the same fPLL to drive logic in the FPGA fabric, you can enable another fPLL output to drive your FPGA logic.

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