Why does the q output of my SCFIFO show incorrect values after assertion of the synchronous clear (sclr) signal during RTL simulation?

Due to a problem in the Quartus® II software, the SCFIFO simulation model may behave incorrectly during RTL simulation. After asserting the sclr signal, the q output of the SCFIFO incorrectly drives all 0's for SCFIFO megafunctions with registered outputs or all X's for SCFIFO megafunction with unregistered outputs.

As documented in the SCFIFO and DCFIFO Megafunction User Guide (PDF), after assertion of the sclr signal the q output should maintain the last value for SCFIFO megafunctions with registered outputs or display the first data word for SCFIFO megafunctions with unregistered outputs. Gate-level simulation of the SCFIFO behaves correctly.