Article ID: 000084185 Content Type: Troubleshooting Last Reviewed: 11/20/2015

Generate Example Design Button May Invoke a Qsys Error Message Under Certain Circumstances

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When an Arria 10 EMIF IP is added to a Qsys system from the Qsys IP Catalog, activating the Generate Example Design button in the IP parameter editor may cause the following Qsys error message to appear: The example design cannot be generated when there are errors. The errors mentioned are system-level connectivity errors which are shown in the Qsys messages window; these errors are not related to the IP example design.

    Resolution

    The workaround for this issue is to generate the example design by invoking the EMIF IP parameter editor from the Quartus IP Catalog.

    This problem will be fixed in a future version.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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